The present invention relates to a distance measuring apparatus and a computer readable storage medium for measuring a distance from an object of measurement, preferably applicable to an AF mechanism of a camera.
Conventionally, a distance measuring apparatus which performs triangulation as distance measurement by projecting spot light on a measurement object and receiving reflected light from the object, as shown in FIG. 6, is well known. That is, an infrared light emission diode (IRED) 81 projects spot light via a projection lens 82 on a measurement object 83, and reflected light from the object is received by a position sensitive device (PSD) 85 via a photoreception lens 84. The PSD 85 outputs signals A and B corresponding to a photoreception position, from both terminals. The photoreception position at the PSD 85 is detected by respectively measuring the signals A and B, and the distance from the measurement object 83 is obtained.
However, the conventional distance measuring apparatus in FIG. 6 has the following problems. That is, in consideration of S/N ratio, noise occurred from the resistance of the amplifier of a signal processor (both not shown) and the PSD is mixed with each synchronous integration in a faint signal, accordingly, to increase a signal component, a distance measuring block constituted with the projection lens 82, the photoreception lens 84 and the like must be enlarged and/or the power of the IRED 81 must be increased, and the distance measuring apparatus cannot be downsized without difficulty.
Further, to widen a distance measuring range, the PSD 85 must be lengthened. However, if the PSD 85 is long, a change rate of distance decreases in the obtained signals A and B, thus the precision in position detection is lowered.
Accordingly, a distance measuring apparatus to perform triangulation as distance measurement by projecting a spot pulse to a measurement object and receiving reflected light from the object, Japanese Published Examined Patent Application No. Hei 5-22843 proposes a distance measuring apparatus which circulates and integrates stored charge in a CCD, at least partially ring shaped, and performs skimming operation to eliminate a predetermined amount of charge of extraneous light component other than the spot light component.
Further, Japanese Published Unexamined Patent Application No. Hei 9-42955 proposes a distance measuring apparatus having the above construction, and further comprising an electronic shutter function (ICG) to control a signal charge amount from each sensor pixel, so as to prevent saturation of output potential.
The distance measuring apparatus proposed by the above-described Japanese Published Unexamined Patent Application No. Hei 9-42955 will be described with reference to FIGS. 7 and 8.
In FIG. 7, a sensor array 41 comprises N sensor blocks S.sub.1, S.sub.2, S.sub.3, . . . , S.sub.N as shown in FIG. 8. Signal charge photoelectric-converted by the respective sensor blocks S.sub.1, S.sub.2, S.sub.3, . . . , S.sub.N are integrated by an integration unit 42.
A clear unit 43 driven by an ICG signal is a so-called electronic shutter comprising a gate circuit. The clear unit 43 has a function to prevent overflow at the integration unit 42 by eliminating a predetermined amount of charge from the integration unit 42, and a function to initialize the integration unit 42 by eliminating all the charge from the integration unit 42.
A storage unit 44 driven by a signal ST is provided in parallel to the sensor array 41. The storage unit 44 temporarily holds charge. A shift unit 45 driven by a signal SH transfers the charge stored in the storage unit 44 to a 2N-stage linear CCD 46 as a charge transfer unit. The linear CCD 46 is connected to a 2N-stage ring CCD 47 as a charge transfer unit. In these linear CCD 46 and the ring CCD 47, each stage comprises a 2-phase CCD driven by a 2-phase clock. Note that each stage may comprise a 3-phase CCD, 4-phase CCD or the like.
A skimming unit 48 provided in the ring CCD 47 eliminates a predetermined amount of charge from a corresponding CCD on the ring CCD 47. A voltage buffer circuit 49 generates a voltage corresponding to the amount of charge stored in a corresponding CCD on the ring CCD 47. A skim judgment unit 50 compares an output voltage from the voltage buffer circuit 49 with a skim judgment voltage, and outputs a judgment signal.
A controller 51 generates shift timing signals (ST and SH) and transfer clock signals for the linear CCD 46 and the ring CCD 47, and outputs the signals. Further, the controller 51 inputs the skim judgment signal from the skim judgment unit 50 and outputs a control signal for the skimming unit 48 in correspondence with the input skim judgment signal, further, outputs a control signal for a reset pulse generator 52 which generates an ICG pulse.
The distance measuring apparatus having the above construction performs skim judgment using the voltage output from the voltage buffer circuit 49 corresponding to the amount of stored charge in the ring CCD 47, prior to full-scale signal storing operation in the ring CCD 47, and if the level of its potential is at a level requiring skimming operation, the controller 51 changes reset timing at the clear unit 43 as the ICG gate, to control integration period of the integration unit 42 not to cause overflow.
FIG. 9 shows the relation between the skim judgment potential and the skimming amount and the influence of ICG control, in the apparatus in FIG. 7. In FIG. 9, a reference potential is at a potential level upon reset of the ring CCD (i.e., when no charge is stored in the ring CCD). In the CCD, as charge is stored, the potential is lowered, accordingly, the skim judgment potential is set to a lower level than the reference potential. The skimming amount skimmed by the skimming unit 48 includes a predetermined difference due to variation of potential of the skimming unit 48 itself, further, the skim judgment potential includes a difference. To prevent disappearance of signal from the ring CCD 47 upon skimming operation, the potential level of the skimming amount is set to a lower level than the skim judgment potential.
In the apparatus in FIG. 7, the ring CCD 47 is reset, and storing operation is made twice, then the integration unit 42 performs ICG control from the result of skim judgment on the output voltage from the ring CCD 47. Note that in the apparatus in FIG. 7, the output voltage from the ring CCD 47 after two storing operations after the reset of the ring CCD 47 is used, however, the output voltage after three or more storing operations may be used in accordance with the relation between the skimming amount and the skim judgment potential.
FIG. 9A shows a case where the luminance is comparatively high. In this case, a voltage drop amount V.sub.Q1 due to the first storing operation in the ring CCD 47 is greater than the amount of one skimming operation. In this prior art, skim judgment is not performed upon first storing operation after reset of the ring CCD 47, and the second storing operation is performed. Then, the output potential of the buffer circuit 49 is lower than the skim judgment potential. Then, the skimming unit 48 performs skimming so as to set the potential level of the ring CCD 47 to V.sub.1. Further, from the result of skim judgment, reset timing by the ICG pulse is changed. In this case, the integration period of the integration unit 42 is reduced in half. Accordingly, the amount of stored charge is V.sub.Q1 /2 From the next storing operation.
In this manner, in the apparatus in FIG. 7, in a case where the ring CCD 47 is reset and charge storing operation is performed twice, if the potential of the ring CCD 47 after the second charge storing operation is equal to or lower than the skim judgment potential, the timing of reset pulse is controlled so as to reduce the integration period of the integration unit 42 in half. By this arrangement, the amount of stored charge after the next charge storing operation becomes V.sub.Q1 /2. Further, as the skimming operation is performed from the subsequent charge storing operation, the output voltage from the voltage buffer circuit 49 is maintained at a level not to cause saturation.
FIG. 9B shows a case where the luminance is at about an intermediate level. In this case, the voltage drop amount V.sub.Q2 due to the first storing operation in the ring CCD 47 is somewhat less than the amount of one skimming operation. By the second storing operation, the output voltage from the voltage buffer circuit 49 is lower than the skim judgment potential. Then, the skimming unit 48 performs skimming to set the potential level of the ring CCD 47 to V.sub.2. Further, from the result of skim judgment, the reset timing of the ICG pulse is changed to reduce the integration period of the integration unit 42 in half. Accordingly, the amount of stored charge in the ring CCD 47 is V.sub.Q2 /2 from the next storing operation.
In this case, the ring CCD 47 is reset and charge storing operation is performed twice, then the potential of the CCD 47 in the second storing operation is compared with the skim judgment potential, and the timing of the reset pulse is controlled so as to reduce the integration period of the integration unit 42 in half. Accordingly, the amount of stored charge in one storing operation reduces to V.sub.Q2 /2. Further, as the skimming operation is performed in the subsequent operations, the output voltage from the voltage buffer circuit 49 is maintained at a level not to cause saturation.
FIG. 9C shows a case where the luminance is comparatively low. In this case, the voltage drop amount V.sub.Q2 due to the first storing operation in the ring CCD 47 is considerably less than the amount of one skimming operation. Then, after the second storing operation, the output voltage from the voltage buffer circuit 49 is still higher than the skim judgment potential, and by the third storing operation, the output voltage from the voltage buffer circuit 49 becomes lower than the skim judgment potential. Then, after the third storing operation, the skimming unit 48 performs skimming to set the potential level of the ring CCD 47 to V.sub.3. At this time, the reset timing of the ICG pulse is not changed. Accordingly, the amount of stored charge in the ring CCD 47 from the subsequent storing operation remains V.sub.Q3.
In this case, the ring CCD 47 is reset and the charge storing operation is performed twice, then the potential of the ring CCD 47 is compared with the skim judgment potential. As the timing of the reset pulse is controlled so as not to change the integration period of the integration unit 42, the amount of stored charge in one storing operation thereafter remains V.sub.Q3. However, as the luminance is comparatively low and the amount of stored charge V.sub.Q3 by one storing operation is considerably less than the amount of one skimming, and the skimming operation is performed in the subsequent storing operations, the output voltage from the voltage buffer circuit 49 is maintained at a level not to cause saturation.
Next, the operation timing of the distance measuring apparatus in FIG. 7 will be described with reference to FIGS. 10A and 10B.
FIG. 10A is a timing chart in a case where the integration period of the integration unit 42 is the maximum. A signal IRCLK indicates ON and OFF states of the infrared light emission diode (IRED). When the signal IRCLK is at a high level, the IRED is in the ON state. The ICG pulse is a signal to control the reset timing of the clear unit 43 (hereinafter referred to as an "ICG gate 43"). When the ICG pulse is at a high level, the charge is eliminated from the integration unit 42. An ST pulse is a shift pulse to the storage unit 44. When the ST pulse is at a high level, the charge is shifted from the integration unit 42 to the storage unit 44. An SH pulse is a shift pulse to the linear CCD 46. When the SH pulse is at a high level, the charge is shifted from the storage unit 44 through the shift unit 45 to the linear CCD 46.
First, immediately after the signal IRCLK became OFF, the ICG gate 43 is reset by the ICG pulse a. Then, signal charge (extraneous light) corresponding to the OFF period of the IRED is shifted from the integration unit 42 to the storage unit 44, by the ST pulse b immediately before the signal IRCLK becomes ON after a period T.sub.1, further, shifted from the storage unit 44 to the linear CCD 46 by the SH pulse c immediately before the signal IRCLK becomes OFF. Next, immediately after the signal IRCLK became ON, the ICG gate 43 is reset by the ICG pulse d. Then, signal charge (extraneous light+signal component) corresponding to the ON period of the IRED is shifted from the integration unit 42 to the storage unit 44, by the ST pulse e immediately before the signal IRCLK becomes OFF after a period T.sub.1, further, shifted from the storage unit 44 to the linear CCD 46 by the SH pulse f immediately after the signal IRCLK has become OFF.
FIG. 10B is a timing chart in a case where the integration period in the integration unit 42 is the half of the period in FIG. 10A. In this case, the timings of the ST pulse and SH pulse other than the ICG reset pulse are the same as those in FIG. 10A. The ICG reset pulse is at the high level at approximately mid-term of the ON and OFF periods of the signal IRCLK, so as to reduce the integration period of the integration unit 42 to the half of the integration period in FIG. 10A.
First, immediately after the half of the OFF period of the signal IRCLK elapsed, the ICG gate 43 is reset by the ICG pulse a. Then, after the period T.sub.1/2, signal charge (extraneous light component) corresponding to the OFF period of the IRED is shifted from the integration unit 42 to the storage unit 44 by the ST pulse b immediately before the signal IRCLK becomes ON, further, shifted from the storage unit 44 to the linear CCD 46 by the SH pulse c immediately before the signal IRCLK becomes OFF.
Next, immediately after the half of the ON period of the signal IRCLK elapsed, the ICG gate 43 is reset by the ICG pulse d. Then, after the period T.sub.1/2, signal charge (extraneous light+signal component) corresponding to the ON period of the IRED is shifted from the integration unit 42 to the storage unit 44, by the ST pulse e immediately before the signal IRCLK becomes OFF, further, shifted from the storage unit 44 to the linear CCD 46 by the SH pulse f immediately after the signal IRCLK became OFF.
In this manner, in this example, the integration period of the integration unit 42 is controlled and the amount of potential change of the ring CCD 47 by one charge storing operation is controlled, by controlling the timing of the ICG pulse.
Next, the operation of the distance measuring apparatus in FIG. 7 will be described in accordance with a flowchart of FIG. 11.
First, when a start signal START is applied to the controller 51 (step S1101), the controller 51 controls the reset pulse generator 52 that generates the reset pulse to the ICG gate 43, so as to generate the ICG pulse, the ST pulse and the SH pulse at the timings in FIG. 10A, and set the integration period of the integration unit 42 to T.sub.1 (step S1102).
Next, after reset of the ring CCD 47, the first ring transfer is performed (step S1103), and the second ring transfer is performed (step S1104). Then, it is determined whether or not the output voltage from the voltage buffer circuit 49 upon completion of the second ring transfer is higher than the skim judgment voltage (whether or not the output potential is lower than the skim judgment potential) (step S1105). If the output voltage is higher than the skim judgment voltage, the controller 51 controls the reset pulse generator 52, to generate the ICG pulse, the ST pulse and the SH pulse at the timings in FIG. 10B, to set the integration period of the integration unit 42 to T.sub.1/2 (step S1106), and continues the storing operation in the ring CCD 47 (step S1107).
If the output voltage is lower than the skim judgment voltage, the timings of the ICG pulse, the ST pulse and the SH pulse are not changed, and the storing operation in the ring CCD 47 is continued (step S1107).
As described above, in the distance measuring apparatus in FIG. 7, the timing of the ICG reset pulse is controlled to set the integration period of the integration unit 42 in half, based on the potential of the ring CCD 47 upon second charge storing operation. Accordingly, even if the luminance is comparatively high and the amount of potential change of the ring CCD 47 by one charge storing operation is greater than the skimming amount, the potential of the ring CCD 47 upon the second charge storing operation is reliably lower than the skim judgment potential. As the amount of potential change of the ring CCD 47 becomes the half from the subsequent charge storing operation, the output voltage almost does not reach a saturation level even if the charge storing operation is continuously performed. Further, the size of the apparatus in FIG. 7, which can be smaller than that of the apparatus in FIG. 6, performs distance measurement with high precision.
However, the distance measuring apparatus in FIG. 7 proposed by the above-described Japanese Published Unexamined Patent Application No. Hei 9-42955 has the following problems.
The storing period is shortened by the ICG control, however, the ON and OFF periods of the IRED are the same. Accordingly, other than the charge storing period, a period to turn the IRED ON occurs, which wastes electric power.
Further, to shorten the storing period is to reduce the amount of signal charge corresponding to an extraneous light component when the luminance is high, and to reduce the amount of signal charge, corresponding to a reflected light component from the object of distance measurement in the IRED light, which can be stored in one storing operation in the ring CCD. Thus, it takes more time to store signal charge necessary for distance measurement calculation. That is, the distance measurement period increases.